1. Field of the Invention
The present invention relates to a semiconductor integrated circuit and particularly to a layout of CMOS type SRAM cells.
2. Description of Related Art
SRAM that configures a memory cell with six transistors can be formed in a standard semiconductor CMOS process and is widely used for system LSI and the like. A conventional SRAM memory cell is comprised of six transistors, which are two NMOS driver transistors, two NMOS transfer transistors and two PMOS load transistors.
Japanese Unexamined Patent Publication No. 2003-115551 (Satomi et al.) discloses a technique to form one each of NMOS driver transistor and NMOS transfer transistor in a first and a second P-well region. It also discloses that two PMOS load transistors are formed in one N-well region.
Meanwhile in recent years as elements become finer, soft error phenomena are reported to occur that causes an inversion of logical data stored in a memory cell due to an influence of radiation such as neutrons from cosmic radiation that reach on the ground. Moreover the influence of radiation further causes a multi-bit error in which a plurality of cells generate an error simultaneously. For this reason, a technique to address such multi-bit error is reported in for example, “Circuit Techniques for Low-Power SRAM”, Osada et al., The Institute of Electronics, Information and Communication Engineers, Technical Report of IEICE, 2004-4.
Moreover in a SRAM cell, retention stability of data is quantitatively provided by a characteristic curve which is created by reversing input and output transfer characteristic curves of inverters and then superimposing the reversed curves on original curves. The larger an area bounded by the two characteristic curves, the more stable data can be retained. A size of this area is referred to as Static Noise Margin (SNM). SNM depends on input logic threshold of an inverter that constitutes SRAM. Accordingly SNM depends on current drive capability (for instance threshold voltage and size of MOSFET) of MOS transistors that constitute the SRAM cell. For example, when an ability of a transfer transistor becomes higher as compared to that of a driver transistor, a level of a bit line can be easily transmitted to a memory node. Since noise on the bit line can be also easily transmitted, it could result in a decrease of SNM, generating a bias in a stability point, and cell data being easily destroyed. For this reason, a transfer transistor is usually designed to have an inferior capability than a driver transistor.
To maintain data retention characteristic of a SRAM memory cell, drive capability of a NMOS driver transistor must be better than that of a NMOS transfer transistor. A technique described by Satomi et al. differentiates between the drive capability of a transfer transistor and that of a driver transistor by having a different implanted ion dose or gate length. Additionally in this technique, diffusion layers and electrodes are shaped in rectangle from an aspect of securing SMN and yield.
Techniques disclosed in Japanese Unexamined Patent Publication No. 10-162581 (Tei et al.) and Japanese Unexamined Patent Publication No. 11-232878 (Michael et al.) use PMOS transistors as transfer transistors. However a layout for the techniques is neither clearly identified nor does the technique include a resolution against the above soft error.
For a SRAM memory cell that induces a difference in drive capability by differentiating a gate length of a driver transistor from that of a transfer transistor as described by Satomi et al., there could be a difficulty in reducing cell area due to nonuniformity in its pattern. It could also reduce accuracy in microfabrication. As a countermeasure for the soft error in a conventional SRAM memory cell, there is a known method to have an error correction circuit from an aspect of circuit technology. There are other known methods from an aspect of process device to add extra capacity to cell node, adjust substrate impurity concentration and use a SOI substrate. However it has now been discovered that no technique has considered over both of a layout in view of processing accuracy and a reduction in charge collection of cell node diffusion layer on a radiation incidence.